The lighthouse deck is based on an iCE40UP5K FPGA. The FPGA boots from an SPI flash to the bootloader, it is then able to boot to another configuration image. The bootloader gives access to the SPI memory and to a boot command to boot the user image. This allows the deck to be updated easily from the Crazyflie or from the auxiliary serial port.

The bootloader protocol is inspired by the TinyFpga USB bootloader but implemented on serial port and I2C bus.

There is two UARTs on the deck, UART0 on te Crazyflie deck interface and UART1 on 2.54mm soldering pads available for external communication. The bootloader is available on both UART. The UARTs are setup at a baudrate of 115200.

When using the UART, commands are sent on the RX line and answer will be sent back by the bootloader on the TX line. Since the bootloader and the Flash SPI bus is working much faster than the UART, there is no need for flow control.

To make sure the boorloader is waiting for a command, a break condition can be sent to the UART to reset the bootloader state. This is good to do before sending the first command in order to make sure the bootloader is not currently in the middle of a command.

Both UART are disabled at startup, this means that the bootloader will ignore all data and break condition coming from them. To enable an UART send the byte “0xBC”. This will enable the UART and reset the bootloader state.

Since 0xBC is not an implemented command. The suggested sequence in order to start the communication is sending “Break condition” and then “0xBC”. This will ensure the UART is enabled and the bootloader is ready to receive the next command.